1. Technical Field
The present invention relates to a multi-level dynamic memory device, and more particularly, to a multi-level dynamic memory having an increased sensing margin.
2. Description of the Related Art
In recent years, various methods of storing more information in a limited wafer area have been developed. For example, sophisticated lithography methods and sophisticated lithography devices have been developed and used to manufacture more memory cells in a limited wafer area. In another method, one or more bits are stored in one memory cell so as to raise the degree of integration per unit area of the dynamic memory device. It is known that this method can be implemented with a multi-level dynamic memory device.
A conventional multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first sense amplifiers that are connected between the main bit line pair, second sense amplifiers that are connected between the sub-bit line pair, and first and second coupling capacitors that are cross-coupled between the main bit line pair and the sub-bit line pair.
In such a multi-level dynamic memory device, a sensing margin is reduced due to the reasons described below. Hereinafter, a case will be exemplified in which memory cells to be read are connected to one of the main bit line pair.
Since the first and second coupling capacitors are cross-coupled between the main bit line pair and the sub-bit line pair, when the first sense amplifier develops a voltage between the main bit line pair, a voltage between the sub-bit line pair varies in an opposite direction. Accordingly, when capacitance of each of the first and second coupling capacitors is too small, a “10” sensing margin is reduced, and when it is too large, a “11” sensing margin is reduced.
When a restoring process is performed in the conventional multi-level dynamic memory device, the main bit line pair and the sub-bit line pair share a charge, and thus the restoring process is performed. Accordingly, when the charge is shared, as capacitance of the sub-bit line pair becomes half of total capacitance between the capacitance of the main bit line pair and the capacitance of the cell capacitor, a restored level becomes more accurate. However, since the capacitance of a cell capacitor in a memory cell was much smaller than that of a bit line in the 1990s, the capacitance of the cell capacitor in the memory cell was ignored, and the lengths of the main bit line pair and the sub-bit line pair were set in a 2:1 relationship. However, in recent years, with the development of cell capacitor manufacturing technologies, the capacitance of the cell capacitor has increased to become about one third of the capacitance of the bit line, and thus, the capacitance of the cell capacitor cannot be ignored. That is, the sensing margin is reduced due to the capacitance of the cell capacitor.